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On the Way to CDi4
Lake Erie datalogging/control operations went digital in 2011 after the introduction of the prototype P7MAIN board and associated charger and memory boards. Five systems were built by June 2011, some firmware bugs were subsequently discovered and corrected, all are alive and well today. The design is actually a set of three boards, a main board plus a charger and memory boards. P7MAIN original combined layers design and individual layers design, charger combined layers design and individual layers design, memory board combined layers and individual layers. Some shortcomings in the original have been addressed in the new CDi3.P7 and CDi3.LE boards. These two additional boards are meant to take care of lake Erie operation needs as they manifest now, in the near future, or even later. The CDi3.P7 takes care of things now, the CDi3.LE board takes care of things later, and as a result P7MAIN has been deprecated and will never be built again. The two new boards are much the same as the original but have several enhancements as explained below:
  1. Clock increase from 6.144MHz to 7.373MHz resulting in a maximum baud rate of 115.2K for both communication channels.
  2. Ability to use the newer DS1553 RTC, since the DS1386 is now obsolete but still available in the aftermarket.
  3. Design preserves the original 8-channel analog circuitry, multiplexer is not used in digital modes, ADC only there to read the battery voltage.
  4. Added a Bluetooth wireless interface to the main communications channel.

Once operation of both boards has been verified, the CDi4 will be built as a general purpose industrial class controller as per lake Erie roadmap, the CDi4 is extremely unlikely to ever be used in the lake.

CDi4 Boards
CDi4 in active development since August 2015, component boards will be added in this section as the work progresses. Two memory boards have been added as of mid-June 2016, main board, charger, and keyboard/display boards yet to be created...
CDi4.M1 Storage Memory/EEPROM Board
CDi4.M2 Storage Memory/EEPROM Board
CDi4 Memory Module 1
  • Board status: designed June 2016, not built yet.
  • Doubles the CDi3 storage Static RAM, SRAM, to 2 Mbytes.
  • Accommodates 64k x 8 and 128k x 8 EEPROMS in 32-pin DIP packages.
  • Board pdf: layers combined, board pdf: layers on separate pages.
CDi4 Memory Module 2
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Copyright © 1991-2018 AdamG Last Update: Friday, March 02, 2018 12:52:08 PM